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E2E1016-27-Y6
Semiconductor MSM65524A/65P524
Semiconductor 8-Bit Microcontroller with A/D Converter
This version: Jan. 1998 MSM65524A/65P524 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM65524A is a high-performance 8-bit microcontroller that employs OKI original nX-8/ 50 CPU core. With a minimum instruction execution time of 400 ns (10MHz clock), the MSM65524A is capable of high-speed processing, and includes 16K bytes of program memory, 384 bytes of data memory, timers, serial ports, an A/D converter and PWMs on chip. Also available are the MSM65P524, which replaces the on-chip program memory with one-time PROM, and the MSM65X524A, which uses the external program memory.
FEATURES
* Operating range Operating frequency Operating voltage Operating temperature * Memory space Internal program memory Internal data memory * Minimum instruction execution time * Powerful instruction set : 0 to 10MHz (VDD=4.5 to 5.5V) 0 to 5MHz (VDD=2.7 to 5.5V) : 2.7 to 5.5V : -40 to +85C : 64K bytes : 16K bytes : 384 bytes : 400ns @ 10 MHz : 83 basic instructions 8/16-bit operation instructions Bit manipulation instructions Compound function instructions : 8 8 AE 16 16 / 8 AE 16 ... 8 : 5 ports 8 bits 1 port 4 bits : 1 port 8 bits : 8-bit auto-reload timer 2 16-bit auto-reload timer 1 Watchdog timer 1 : Time base counter 1 16-bit free-running counter 1 : 1 channel : 2 channels : Shift register 1 Serial port with baud rate generator (UART/Synchronous) 1 : 8 bits 8 channels : 8 bits 2 channels PWM with auto-reload timer for period setting 1/27
* Abundant addressing modes * Multiplication/division operation functions * I/O port Input-output port Input port * Timers
* Counters * Capture input * Compare output * Serial ports
* A/D converter * PWM
Semiconductor
MSM65524A/65P524
* External interrupts :3 * Interrupt sources : 19 * Package options 64-pin plastic shrink DIP (SDIP64-P-750-1.78) : (Product name: MSM65524A-SS, MSM65P524-SS) 64-pin plastic QFP (QFP64-P-1414-0.80-BK) : (Product name: MSM65524A-GS-BK, MSM65P524-GS-BK) 68-pin plastic QFJ (PLCC) (QFJ68-P-S950-1.27): (Product name: MSM65524A-JS, MSM65P524-JS) indicates the code number.
2/27
BLOCK DIAGRAM
Semiconductor
OSC 0 OSC 1 RESET HSTOP*
ROM (16K bytes) OSC CONT. CPU CORE INST. DEC.
8
EXT.MEM. CONT.
8 8
AD0-7* A8-15* RD WR* ALE EA
8 ALU GMAR PC
BUS CONT.
VDD GND
RAM (384 bytes) TBC WDT T2CK* CAP* CMP0* CMP1* TXD* RXD* PWM0* PWM1* T1OUT* T0CK* GATE* SFTO* SFTI* SFTCK* INT0* INT1* INT2*
T/C IR
8
16-bit TIMER
AR
BR
PSW
SP
LMAR
16-bit FRC CAP1, CMP2
SIO
8-bit PWM2
MUL/DIV
8-bit A/D C 8ch
I/O PORT
8-bit TIMER4**
8-bit SHIFT-REG.
MSM65524A/65P524
P0 P1 P2 P3 P4 P5 P6
INTERRUPT CONT.
VRL VRH AVDD
AGND
AI0*- AI7*
* Secondary functions of ports ** One timer doubles as the SIO baud rate generator, another doubles as a PWM clock source.
3/27
Semiconductor
MSM65524A/65P524
PIN CONFIGURATION (TOP VIEW)
P5.0/PWM0 P5.1/PWM1 P5.2 P5.3 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P3.0/T2CK P3.1/CAP P3.2/CMP0 P3.3/CMP1 P3.4/INT2 P3.5/SFTO P3.6/SFTI P3.7/SFTCK RESET P2.0/RXD P2.1/TXD P2.2/INT0 P2.3/INT1/GATE P2.4/T0CK P2.5/HSTOP P2.6/WR P2.7/T1OUT OSC1 OSC0 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD AVDD VRH VRL P6.7/AI7 P6.6/AI6 P6.5/AI5 P6.4/AI4 P6.3/AI3 P6.2/AI2 P6.1/AI1 P6.0/AI0 AGND P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE RD P1.7/A15 P1.6/A14 P1.5/A13 P1.4/A12 P1.3/A11 P1.2/A10 P1.1/A9 P1.0/A8
64-Pin Plastic Shrink DIP
4/27
Semiconductor
MSM65524A/65P524
PIN CONFIGURATION (TOP VIEW) (Continued)
58 P5.1/PWM1
57 P5.0/PWM0
52 P6.7/AI7
54 P6.6/AI6
50 P6.5/AI5
P4.4 P4.5 P4.6 P4.7 P3.0/T2CK P3.1/CAP P3.2/CMP0 P3.3/CMP1 P3.4/INT2
1 2 3 4 5 6 7 8 9
P3.5/SFTO 10 P3.6/SFTI 11 P3.7/SFTCK 12 RESET 13 P2.0/RXD 14 P2.1/TXD 15 P2.2/INT0 16
P2.3/INT1/GATE 17
P2.4/T0CK 18
P2.5/HSTOP 19
P2.6/WR 20
P2.7/T1OUT 21
OSC1 22
OSC0 23
GND 24
P1.0/A8 25
P1.1/A9 26
P1.2/A10 27
P1.3/A11 28
P1.4/A12 29
P1.5/A13 30
P1.6/A14 31
64-Pin Plastic QFP
P1.7/A15 32
63 P4.2 62 P4.1 61 P4.0 60 P5.3 59 P5.2
49 P6.4/AI4 48 P6.3/AI3 47 P6.2/AI2 46 P6.1/AI1 45 P6.0/AI0 44 AGND 43 P0.0/AD0 42 P0.1/AD1 41 P0.2/AD2 40 P0.3/AD3 39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 35 EA 34 ALE 33 RD
55 AVDD
64 P4.3
56 VDD
54 VRH
53 VRL
5/27
Semiconductor
MSM65524A/65P524
PIN CONFIGURATION (TOP VIEW) (Continued)
56 AGND 55 P0.0/AD0
54 P0.1/AD1 53 P0.2/AD2
52 NC 51 P0.3/AD3
50 P0.4/AD4 49 P0.5/AD5
48 P0.6/AD6 47 P0.7/AD7
60 P6.3/AI3 59 P6.2/AI2
58 P6.1/AI1 57 P6.0/AI0
46 EA 45 ALE
P6.4/AI4 61 P6.5/AI5 62 P6.6/AI6 63 P6.7/AI7 64 VRL 65 VRH 66 AVDD 67 NC 68 VDD 1 P5.0/PWM0 2 P5.1/PWM1 3 P5.2 4 P5.3 5 P4.0 6 P4.1 7 P4.2 8 P4.3 9
P4.4 10 P4.5 11
44 RD
43 P1.7/A15 42 P1.6/A14 41 P1.5/A13 40 P1.4/A12 39 P1.3/A11 38 P1.2/A10 37 P1.1/A9 36 P1.0/A8 35 NC 34 GND 33 OSC0 32 OSC1 31 P2.7/T1OUT 30 P2.6/WR 29 P2.5/HSTOP 28 P2.4/T0CK 27 P2.3/INT1/GATE
P4.6 12 P4.7 13
P3.0/T2CK 14 P3.1/CAP 15
P3.2/CMP0 16 P3.3/CMP1 17
NC 18 P3.4/INT2 19 P3.5/SFTO 20
P3.6/SFTI 21 P3.7/SFTCK 22
RESET 23 P2.0/RXD 24
NC: No-connection pin 68-Pin Plastic QFJ (PLCC)
P2.1/TXD 25 P2.2/INT0 26
6/27
Semiconductor
MSM65524A/65P524
PIN DESCRIPTION
Basic Functions
Function Symbol VDD GND Power Supply AVDD AGND VRH VRL OSC0 Oscillation OSC1 RESET EA Control RD ALE PORT 0 O O I/O O I I Type -- -- -- -- -- -- I +5V digital power supply 0V digital ground +5V analog power supply 0V analog ground +5V analog reference voltage 0V analog reference voltage System clock input pin. Quartz oscillator or ceramic oscillator is connected between OSC0 and OSC1. For external clock, input at OSC0, leaving OSC1 open. System clock output pin System reset input (program starts from address 0040H); internal pull-up resistance Program memory select input pin. "L" level input for external program memory; "H" level input for internal program memory. Read strobe signal during external memory access Address latch signal during external memory access 8-bit Input-output port During external memory access, becomes address/data bus for address output, instruction fetch or data read/write along with ALE, RD and WR pins. 8-bit Input-output port Address bus during external memory access 8-bit Input-output port 3. Secondary functions shown in following table are added for ports 2 and 3. 4-bit Input-output port Secondary functions shown in following table are added for port 5. 8-bit Input port Functions as analog input channel during A/D conversion. Description
PORT 1 Port PORT 2 PORT 3 PORT 4 PORT 5 PORT 6
I/O I/O
I/O I
7/27
Semiconductor Secondary Functions
Symbol RXD Type I/O Description
MSM65524A/65P524
P2.0 secondary function UART: Input pin for serial port receive data. Synchronous: Input/output pin for serial port transmit/receive data. P2.1 secondary function UART: Output pin for serial port transmit data. Synchronous: Output pin for serial port synchronizing clock. P2.2 secondary function External interrupt 0 input pin. P2.3 secondary functions External interrupt 1 input pin. Also used as input pin for gate signal for timer 0 count enable/disable. P2.4 secondary function Timer 0 external clock input pin. P2.5 secondary function Hard stop mode input pin; stops system clock oscillation with "L" level input. P2.6 secondary function Write strobe signal output pin during external data memory access. P2.7 secondary function Output pin for signal that 2-divided timer 1 overflow. P3.0 secondary function Timer 2 external clock input pin. P3.1 secondary function Capture trigger input pin. P3.2 secondary function Compare output channel 0 output pin. P3.3 secondary function Compare output channel 1 output pin. P3.4 secondary function External interrupt 2 input signal. P3.5 secondary function Shift register data output pin. P3.6 secondary function Shift register data input pin. P3.7 secondary function Shift register synchronizing clock input/output pin. P5.0 secondary function PWM channel 0 output pin. P5.1 secondary function PWM channel 1 output pin.
TXD
O
INT0 INT1/GATE
I I
T0CK HSTOP WR T1OUT T2CK CAP CMP0 CMP1 INT2 SFTO SFTI SFTCK PWM0 PWM1
I I O O I I O O I O I I/O O O
8/27
Semiconductor Port Circuit Configuration
Type Port Circuit Configuration
MSM65524A/65P524
Electrical Characteristics (VDD=5V)
Data Bus
P0D
PORT0
"H" Input Voltage: * VIH=2.4V "L" Input Voltage: * VIL=0.8V "H" Output Voltage: * VOH=3.75V * IOH=-400mA
1
P0.0/AD0 to P0.7/AD7
P0 DIR
External Memory Control
"L" Output Voltage: * VOL=0.4V * IOL=3.2mA "H" Input Voltage: * VIH=2.4V "L" Input Voltage: * VIL=0.8V "H" Output Voltage: * VOH=3.75V * IOH=-200mA
Data Bus
P1D
PORT1
2
P1.0/A8 to P1.7/A15
P1 DIR
External Memory Control
"L" Output Voltage: * VOL=0.4V * IOL=1.6mA
"H" Input Voltage: * VIH=2.4V "L" Input Voltage: * VIL=0.8V Data Bus
P2.0/RXD, P2.1/TXD, P2.6/WR, P2.7/T1OUT, P3.2/CMP0, P3.3/CMP1, P3.5/SFTO, P3.7/SFTCK, P5.0/PWM0, P5.1/PMW1
Px MOD
3
Secondary Output Function
PORTx
PxD
P2.6/WR "H" Output Voltage: * VOH=3.75V * IOH=-400mA "L" Output Voltage: * VOL=0.4V * IOL=3.2mA Ports other than P2.6/WR "H" Output Voltage: * VOH=3.75V * IOH=-200mA "L" Output Voltage: * VOL=0.4V * IOL=1.6mA
Px DIR
Secondary Input Function (x=2 to 5)
9/27
Semiconductor Port Circuit Configuration (Continued)
Type Port Circuit Configuration
MSM65524A/65P524
Electrical Characteristics (VDD=5V)
4
P2.2/INT0, P2.3/INT1/GATE, P2.4/T0CK, P2.5/HSTOP, P3.0/T2CK, P3.1/CAP, P3.4/INT2, P3.6/SFTI, P4.0 to P4.7, P5.2 to P5.3
Data Bus
PxD
PORTx
"H" Input Voltage: * VIH=2.4V "L" Input Voltage: * VIL=0.8V
Px DIR
Secondary Input Function "H" Output Voltage: * VOH=3.75V * IOH=-200mA "L" Output Voltage: * VOL=0.4V * IOL=1.6mA
(x=2 to 5)
5
P6.0/AI0 to P6.7/AI7
Data Bus
"H" Input Voltage: * VIH=2.4V "L" Input Voltage: To A/D Converter * VIL=0.8V PORT6
10/27
Semiconductor
MSM65524A/65P524
MEMORY MAPS
General Memory Space 0FFFFH
External Memory
Local Memory Space 1FFH Page 1
Data Memory
4000H
Program Memory
100H
SFR
100H
Vector Call Table Area
80H Internal Memory
Data Memory
Page 0
80H 40H 20H 0
Program Memory Interrupt Vector Table Area Vector Call Table Area
40H 30H 20H 10H 0
Local Register Set 3 Local Register Set 2 Local Register Set 1 Local Register Set 0
11/27
Semiconductor
MSM65524A/65P524
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Output Voltage Analog Reference Voltage Analog Input Voltage Power Dissipation Storage Temperature Symbol VDD=AVDD VI VO VRH, VRL VAI PD TSTG Ta=25C per package -- Ta=25C GND=AGND=0V Condition Rating -0.3 to 7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 400 -55 to +150 mW C V Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Analog Supply Voltage Analog Reference Voltage Analog Input Voltage Memory Hold Voltage Operating Frequency *1 External Clock Operating Frequency Operating Temperature Symbol VDD AVDD VRH VAI VDDMH fOSC fEXTCLK Top Condition Refer to Figure 1. VDD=AVDD=VRH GND=AGND=VRL=0V fOSC=0 Hz Refer to Figure 1. Refer to Figure 1. -- Range 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 0 to VDD 2.0 to 5.5 1 to 10 0 to 10 -40 to +85 MHz MHz C V Unit
*1 This is due to the standard of a crystal oscillator or resonator.
Ta=-40 to +85C 10
fOSC, fEXTCLK (MHz)
8 6 5 4 2 1 2 3 2.7 4 VDD (V) 5 5.5 6 Oscillator Frequency > 1MHz
Figure 1. Power Supply Voltage vs. Operating Frequency
12/27
Semiconductor
MSM65524A/65P524
ELECTRICAL CHARACTERISTICS
DC Characteristics 1 (VDD=4.5 to 5.5V)
(GND=0V, Ta=-40 to +85C) Parameter "H" Input Voltage 1 "H" Input Voltage 2 "L" Input Voltage "H" Output Voltage 1 "H" Output Voltage 2 "L" Output Voltage 1 "L" Output Voltage 2 Input Leakage Current 1 Input Leakage Current 2 "L" Input Current Input Capacitance Static Current Consumption Dynamic Current Consumption
*3 *4 *3 *4 *5 *6 *7 *1 *2
Symbol VIH1 VIH2 VIL VOH1 VOH2 VOL1 VOL2 ILI1 ILI2 IIL CI IDDS IDD
Condition -- -- -- IOH=-200mA IOH=-400mA IOL=1.6mA IOL=3.2mA VI=VDD/0V VI=VDD/0V VI=0V f=1MHz, Ta=25C 5V, stop mode
*8
Min. 2.4 0.7VDD -0.3 0.75VDD 0.75VDD -- -- -- -- -40 -- -- --
Typ. -- -- -- -- -- -- -- -- -- -120 5 -- 20
Max. VDD+0.3 VDD+0.3 0.8 -- -- 0.4 0.4 1 10 -400 -- 50 40
Unit
V
mA
pF mA mA
10MHz, 5V, no load Refer to Figure2
*1 *2 *3 *4 *5 *6 *7 *8
Excluding OSC0 and RESET OSC0 and RESET Excluding P0, ALE, RD, P2.6/WR P0, ALE, RD, P2.6/WR EA, P6 Excluding RESET, EA, P6 RESET The ports set for input mode are VDD or 0V and the ports except these are no load.
13/27
Semiconductor DC Characteristics 2 (2.7VDD<4.5V)
MSM65524A/65P524
(GND=0V, Ta=-40 to +85C) Parameter "H" Input Voltage 1 "H" Input Voltage 2 "L" Input Voltage "H" Output Voltage 1 "H" Output Voltage 2 "L" Output Voltage 1 "L" Output Voltage 2 Input Leakage Current 1 Input Leakage Current 2 "L" Input Current Input Capacitance Static Current Consumption Dynamic Current Consumption
*3 *4 *3 *4 *5 *6 *7 *1 *2
Symbol VIH1 VIH2 VIL VOH1 VOH2 VOL1 VOL2 ILI1 ILI2 IIL CI IDDS IDD
Condition -- -- -- IOH=-10mA IOH=-20mA IOL=10mA IOL=20mA VI=VDD/0V VI=VDD/0V VDD=2.7 to 3.3V VI=0V f=1MHz, Ta=25C 3V, stop mode
*8
Min. 0.5VDD+0.2 0.6VDD+0.4 -0.3 0.75VDD 0.75VDD -- -- -- -- -40 -- -- --
Typ. -- -- -- -- -- -- -- -- -- -120 5 -- 6
Max. VDD+0.3 VDD+0.3
0.15VDD+0.1
Unit
-- -- 0.1 0.1 1 10 -240 -- 25 15
V
mA
pF mA mA
5MHz, 3V, no load Refer to Figure 2
*1 *2 *3 *4 *5 *6 *7 *8
Excluding OSC0 and RESET OSC0 and RESET Excluding P0, ALE, RD, P2.6/WR P0, ALE, RD, P2.6/WR EA, P6 Excluding RESET, EA, P6 RESET The ports set for input mode are VDD or 0V and the ports except these are no load.
14/27
Semiconductor
MSM65524A/65P524
10MHz 50 40
IDD (mA)
Max.
30 Typ. 20 10 2 3 4 5 VDD (V) 6
6MHz 50 40
IDD (mA)
Max.
30 20 10 2 3 4 5 VDD (V) 6 Typ.
2MHz 50 40
IDD (mA)
30 20 10 2 3 4 5 VDD (V) 6 Ta=-40 to +85C, no load Max. Typ.
Figure 2. Voltage vs. Current
15/27
Semiconductor AC Characteristics * External memory control
MSM65524A/65P524
(VDD=AVDD=VRH=2.7 to 5.5V, GND=AGND=VRL=0V, Ta=-40 to +85C) Parameter Clock Period "L" Clock Pulse Width "H" Clock Pulse Width Clock Period "L" Clock Pulse Width "H" Clock Pulse Width ALE Pulse Width ALE Pulse Delay Time 1 ALE Pulse Delay Time 2 RD Pulse Width RD Pulse Delay Time WR Pulse Width WR Pulse Delay Time "L" Address Setup Time "H" Address Setup Time "L" Address Hold Time Bus Float Time "H" Address Hold Time "H" Address Hold Time Read Data Access Time Read Data Access Time Read Data Hold Time Write Data Setup Time Write Data Hold Time Symbol tC tCLW tCHW tC tCLW tCHW tAW tALD1 tALD2 tRW tRD tWW tWD tLAS tHAS tLAH tLAZ tHAHR tHAHW tRDAA tRDAR tRDH tWDS tWDH CL=100pF VDD=2.7 to 5.5V VDD=4.5 to 5.5V Condition Min. 100 45 45 200 90 90 tC+tCHW-20 tCLW-20 tCLW-20 tC+tCHW-20 tCLW-20 tC+tCHW-40 tCLW-20 tC-40 tC-40 tCLW-20 -- tC-20 tC-20 -- -- 0 tC+tCHW-40 tCLW-20 Max. -- -- -- -- -- -- -- -- -- -- tCLW+20 -- tCLW+40 -- -- -- 20 -- -- tC+tCLW-15 tCHW+10 -- -- -- ns Unit
16/27
Semiconductor
MSM65524A/65P524
tCHW OSC0 tCLW ALE
tC
tAW
tRD RD tRDAR tLAS P0 ADDRESS L tRDAA tHAS P1 tWD WR tLAH tLAZ
tRW
tALD1
tRDH INST or DATA IN
tHAHR ADDRESS H tWW tALD2
tWDS P0 ADDRESS L DATA OUT
tWDH
tHAHW P1 ADDRESS H
17/27
Semiconductor * CPU control
MSM65524A/65P524
(VDD=AVDD=VRH=2.7 to 5.5V, GND=AGND=VRL=0V, Ta=-40 to +85C) Parameter RESET Pulse Width *1 RESET Pulse Width *2 Symbol tRESW1 tRESW2 Condition -- -- Min. 20
*3
Max. -- --
Unit ns --
*1 Excluding power ON, stop mode and hard stop mode. *2 In power ON, stop mode and hard stop mode. *3 Oscillation stabilization time depends on resonator.
RESET Pulse Width
tRESW1, 2 RESET
* Peripheral control 1
Parameter OSC Clock Period External Interrupt Pulse Width External Clock Pulse Width GATE Pulse Width T2 CAP External Clock Pulse Width CAP Pulse Width
(VDD=AVDD=VRH=2.7 to 5.5V, GND=AGND=VRL=0V, Ta=-40 to +85C) Symbol tC tEXIW Condition VDD=4.5 to 5.5V VDD=2.7 to 5.5V Min. 100 200 4 tC Max. -- -- -- Unit
EXI
tT0CW -- tT0GW tT2CW
4 tC 1 tTOCLK *1 4 tC
--
ns
T0
-- --
tCAPW
12 tC
--
*1 tT0CLK : Timer 0 count clock period selected by T0CON.
18/27
Semiconductor
MSM65524A/65P524
tC OSC0 tCLW
1) EXI pulse width
tEXIW INT0-2
2) T0
T0CK
tT0CW
tT0GW GATE
3) T2
tT2CW T2CK
4) CAP
CAP
tCAPW
19/27
Semiconductor * Peripheral control 2
MSM65524A/65P524
(VDD=AVDD=VRH=2.7~5.5V, GND=AGND=VRL=0V, Ta=-40 to +85C) Parameter OSC Clock Period SFTCK Period SFTCK "L" Pulse Width SFT SFTCK "H" Pulse Width SFTCK Setup Time SFTO Hold Time SFTI Setup Time SFTI Hold Time Synchronous Clock Period Synchronous Clock "L" Pulse Width Symbol tC tSFC tSFCLW tSFCHW tSFOS tSFOH tSFIS tSFIH tSIC tSICLW tSICHW tSIOS tSIOH tSIIS tSIIH CL=100pF Condition VDD=4.5 to 5.5V VDD=2.7 to 5.5V Min. 100 200 8 tC 4 tC-20 4 tC-20 tSFCLW-100 tSFCHW-100 100 100 8 tC 4 tC-20 4 tC-20 6 tC-100 2 tC-100 tC+tCLW+100 0 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns Unit
SIO (Clock Synchronous Clock "H" Synchro- Pulse Width nous Output Data Setup Time Mode) Output Data Hold Time Input Data Setup Time Input Data Hold Time
20/27
Semiconductor 1) SFT
tSFC tSFCLW SFTCK tSFCHW
MSM65524A/65P524
tSFOS SFTO tSFIS SFTI
tSFOH
tSFIH
2) SIO (Clock synchronous mode)
tSIC tSICLW TXD tSICHW
tSIOS RXD (transmission) tSIIS RXD (reception)
tSIOH
tSIIH
21/27
Semiconductor A/D Converter Characteristics 1
MSM65524A/65P524
(VDD=AVDD=VRH=5V10%, GND=AGND=VRL=0V, Ta=-40 to +85C) Parameter Resolution Absolute Error Symbol n EL Analog input source impedance RI5kW Condition See the recommended circuit (Fig. 3). Min. -- -- Typ. 8 -- Max. -- +1.5 -1.5 -- -- -- See the measuring circuit (Fig. 4). fOSC=10 MHz -- -- -- -- -- -- 16 0.5 +1.5 -1.5 0.5 -- LSB LSB LSB LSB ms/CH Unit bit LSB
Differential Linearity Error Zero Point Error Full Scale Error Crosstalk Conversion time *
ED EZS EFS ECT tCONV
*
The transition time after the G0 bit goes to "1" is 14.8ms/CH.
A/D Converter Characteristics 2
(VDD=AVDD=VRH=2.7 to 4.5V, GND=AGND=VRL=0V, Ta=-40 to +85C) Parameter Resolution Absolute Error Symbol n EL Analog input source impedance RI5kW Condition See the recommended circuit (Fig. 3). Min. -- -- Typ. 8 -- Max. -- +2 -2 -- -- -- See the measuring circuit (Fig. 4). fOSC=5 MHz -- -- -- -- -- -- 32 1 +2 -2 1 -- LSB LSB LSB LSB ms/CH Unit bit LSB
Differential Linearity Error Zero Point Error Full Scale Error Crosstalk Conversion time *
ED EZS EFS ECT tCONV
*
The transition time after the G0 bit goes to "1" is 29.6ms/CH.
22/27
Semiconductor * Definitions of terms (1)
MSM65524A/65P524
Resolution The minimum distinguishable analog value. For 8 bits, 28=256, i.e. (VRH-VRL) / 256. Linearity Error The variance between the ideal conversion characteristics as an 8-bit A/D converter and actual conversion characteristics (does not include quantatized error). The ideal conversion characteristics refer to steps of the voltage between VRH and VRL into 256 intervals.
(2)
(3)
Differential Linearity Error Indicates the smoothness of the conversion. The width of analog input voltage corresponding to the change by one bit of digital output is 1 LSB = (VRH-VRL) / 256 ideally. The variance between this ideal bit size and bit size at arbitrary point in the conversion range. Zero Scale Error The variance between the ideal conversion characteristics at the switching point of digital output "000H to 001H" and actual conversion characteristics. Full Scale Error The variance between the ideal conversion characteristics at the switching point of digital output "0FEH to 0FFH" and actual conversion characteristics.
(4)
(5)
23/27
Semiconductor
MSM65524A/65P524
VRH
AVDD
0.1 mF VDD +5V
MSM65524A - Analog Voltage Input + R1 0.1 mF AI0-7
+ 47 mF
0V VRL 0.1 mF AGND GND
RI (Analog input source impedance)5kW
Figure 3. Recommended Circuit
- Analog Voltage Input +
5kW AI0 AI1 Crosstalk is defined as the difference of A/D conversion result between supplying the same voltage to AI0 to AI7 and supplying voltage shown in this diagram.
0.1 mF
AI7
VREF or AGND
Figure 4. Crosstalk Measuring Circuit
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Semiconductor
MSM65524A/65P524
PACKAGE DIMENSIONS
(Unit : mm)
SDIP64-P-750-1.78
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin Cu alloy Solder plating 5 mm or more 8.70 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
25/27
Semiconductor
MSM65524A/65P524
(Unit : mm)
QFP64-P-1414-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
26/27
Semiconductor
MSM65524A/65P524
(Unit : mm)
QFJ68-P-S950-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin Cu alloy Solder plating 5 mm or more 4.50 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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